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1. general description 1.1 overview the a710x family is a tamper resistant secure micro controller unit (mcu) family using a dedicated security hardened mx51cpu. nxp semiconductors has a long track record in security mcus. nxp ics had been used in all kind of security applications like bank cards, health insurance cards, electronic passports, pay-tv cards or as embedded secure element in mobile phones. the a710x family features a significantly enhanced secure microcontroller architecture. extended instruct ions for java and c code, linear addressing and high speed at low power are among many other improvements added to the classic 80c51 core architecture. the a710x family supports the following features: ? dedicated mx51 security cpu ? 400 kbit/s i 2 c fast-mode interface ? four wire 2 mbit spi interface ? 111 kbit/s one-wire interface according to ref. 16 (a7103) ? ? 40 ? c to +90 ? c operational ambient temperature (a7102) ? optional on-chip operating system firmware: jcop 2.4.2 (a710xc) ? optional x.509 certificate-based client authentication application pre-installed ? optional on-chip cryptographic library ? nxp glue logic ? nxp secure fetch technology ? active shield ing technology ? asynchronous self-timed handshake technology ? 20 kb eeprom for application-code and data ? 40 ? a typical sleep mode current with i 2 c pads in tristate mode ? 10 ? a max deep sleep mode current with i 2 c pads in tristate mode ? high-performance secured public key infrastructure (pki) coprocessor ? (rsa up to 4096-bit keys, ecc over gf (p) up to 544-bit keys) ? secured 2-key/3-key tr iple-des coprocessor ? secured aes coproce ssor (128-, 192- and 256-bit keys) ? eeprom with min 500,000 cyc les endurance an d min 25 years retention time ? four general-purpose io ports (partly multiplexed with the i 2 c and spi interface) ? broad range of tiny package types, i.e. wlcsp a710x family secure authentication microcontroller rev. 3.5 ? 1 november 2013 ? 195735 product short data sheet company public
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 2 of 20 nxp semiconductors a710x family secure authentication microcontroller the a710x family key benefits: ? complete security platform enabling customized solutions ? field and silicon proven solutions- deployed in numer ous devices and environments ? ensures trust to drive applications in open and closed systems where high level of security is needed ? full solution, ease to integrate, ensuring lower total cost of ownership ? robust cryptographic core, countermeasures and protection of device assets ? powerful cryptographic coprocessors for p ublic and secret key encryption within a low-power, performance optimized design based on nxp semiconductors' handshaking technology. for more detailed information re fer to following document ation 1 : ? hardware data sheet a710x family, secure authentication microcontroller, document number docid 2164xx 2 (see ref. 8 ). the hardware data sheet explains the details of the a710x family product from a h a rdware point of view. it outlines figures like pinning diagram and power consumption but also provides all information needed to develop firmware running on the chip (rom code). 1. these documents are available under nda 2. where xx refers to the last version; e.g. 10 refers to version 1.0
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 3 of 20 nxp semiconductors a710x family secure authentication microcontroller 1.2 cryptographic hardware coprocessors 1.2.1 pki coprocessor the approved and modular pki coprocessor arch itecture supports the trend of increasing rsa keys with faster execution speeds as well as elliptic curve cryptography (ecc) based on gf(p) or gf(2 n ) at best performance. the pki coprocessor supports rsa with an operand length of up to 8-kbit (up to 4- kbit with intermediate storage in ram only). the pki coprocessor supports 192-bit ecc key length that offers the same level of secur i ty as 2048-bit rsa. an ecc gf(2 n ) based signature, using a 163-bit key can be executed in less than 30 ms providing a security level comparable to 1024-bit rsa. the oper and size for ecc is only limited by the 2.5 kb size of the crypto-ram. the pki copr ocessor is easy to use and the flexib le interface provides programmers with the flexibility to implement their own cryptography solutions. 1.2.2 triple-des coprocessor the des widely used for symmetric encryption is supported by a dedicated, high performance, highly attack-r esistant hardware coprocessor. single des and triple-des, based on two or three des keys, can be executed within less than 40 ? s. relevant st andards (iso/iec, ansi, fi ps) and message authentication code (mac) are fully supported. 1.2.3 aes coprocessor the a710x family secure microcontroller platform provides a dedicated high performance 128-bit parallel proce ssing coprocessor to support secu re aes. the implementation is based on fips197 as standardized by the nation al institute for standards and technology (nist), and supports key lengths of 128-bit, 192-bit, and 256-bit with performance levels comparable to des. aes is the next gene ration for symmetric data encryption and recommended successor of des providing a significantly improved security level. 1.3 i 2 c interface the a710x family has an i 2 c interface supporting data rates up to 400 kbit/s operating in fast-mode (fm) as specified in ref. 4 . both operating modes, master and slave are supported. the i 2 c address is configurable by the embedded firmware. 1.4 spi interface the a710x family has a four wire spi slave interf ace supporting data rates up to 2 mbit for full-duplex and synchronous data transfer. 1.5 universal asynchronous receiver/transmitter (uart) the a7103 uses a built-in universal asynch ronous receiver/transmitter (uart) to support a smart card onewire (sc1w) protocol as specified in ref. 16 . the protocol is using a one-wire based physical interface, a uart-based data link layer, an smbus ba sed network layer as well as a mapping layer to convey iso/iec 7816-4 based communication. the uart is software configurable to use any of the four io ports.
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 4 of 20 nxp semiconductors a710x family secure authentication microcontroller 1.6 general-purpose io ports the a710x family has four general-purpose io ports (partly multiplexed with the uart, i 2 c and spi interface) which can be used for any purpose. 1.7 optional on-chip cr yptographic library a secure crypto library providing a broad range of required functions will be available for all a710x devices in order to support customers implementing cryptographic solutions: ? various algorithms ? aes encryption and de cryption using the aes coprocessor ? des and triple-des encryption and decryption using the des coprocessor ? rsa encr y ption and decryption, signatur e generation and verification for straightforward and crt keys up to 4096-bit ? r sa key generation ? ecc o ver gf(p) signature generation and verification (ecdsa) and diffie-hellman ke y exchange for keys up to 544 bits ? ecc over gf(p) key generation ? ecc over gf(2 n ) signature generation and verification (ecdsa) and diffie-hellman key exchange for keys up to 544-bit ? ecc over gf(2 n ) key generation ? sha-1 , sha-224 and sha-256 hash algorithm ? pseu do-random number generator (prng) ? easy to use api for all algorithms ? latest built-in security features to avoid power (spa/dpa), timing and fault attacks (dfa) 1.8 optional on-chip operating system firmware: jcop 2.4.2 (a710xc) the a710x family can execute program code from its internal memories. the rom is used to host program code and data either owned by nxp semiconductors or provided by third-parties (custom rom masked product). nxp semiconductors offers a java card open platform operating system called jcop b a sed on independent, third-party specificat ions, i.e. by oracle, the global platform consortium, the international organization for standards (iso), emv (europay, mastercard and visa) and others. the java card and globalplatform industry standards together ensure ease of ap plication development and application in teroperability for developers. jcop 2.4.2 compliant to java card spec ification v3.0.1 classic as defined in ref. 1 jcop 2.4.2 compliant to global pl atform specification as defined in ref. 2 and ref. 3 .
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 5 of 20 nxp semiconductors a710x family secure authentication microcontroller jcop provides extended support for several industry-specific requirements. this support is given with the jcopx api that comprises followin g functionality: ? extended cryptography support (several algorithms and methods not specified in java card v3.0.1 classic (see ref. 1 ) ? a710xc (jcop 2.4.2 r1): support of io config and control api, implementing methods to reconfigure the default i 2 c slave address, to configure the gpio pin as either input or output pin and the read, set or clear the pin. ? for more detailed information re fer to following document ation 3 : ? user manual jcop 2.4.2 revision 1.0, jc op v2.4.2 revision 1.0 secure a7 mcu operating system, document number 2318xx 4 (see ref. 10 ). the user manual describes jcop for the appl e t developer. it outlines the features available through the java card api. also it explains any additional functionality at the java layer. also, this user manual contains the information on how to order a710x family products. ? administrator manual jcop 2.4.2 revision 1. 0, jcop v2.4.2 revision 1.0 secure a7 mcu operating system, document number 2319xx 4 (see ref. 11 ). ? the administrator manual describes jcop fo r th e administrator of a jcop operating system. this means it explains the pre- personalization process and its specific commands. ? hardware data sheet, a710x fa mily, secure authentication microcontroller, document number 2164xx 4 (see ref. 8 ). the full data sheet explains the details of the a7 10x family product from a hardware point of view. it outlines figures lik e pinning diagram and power consumption. ? a710x family with jcop 2.4.1r1, secure authentication microcontroller, document number 2366xx 4 (see ref. 9 ). the data sheet explains the details of th e a710x family product embedding a jcop 2.4.2 r1 operating system from a hardware point of view. it outlines figures like pinning diagram and power consumption. 1.9 optional x509 certificate-b ased client authentication in addition to the a710x fa mily secure m cu and the java card open platform operating system, the total solution includes an x.509 certificate-based client authentication application. for more detailed information re fer to following document ation: ? application note, device authentication apdu specification, document number 2118xx 4 (see ref. 12 ). the applet user manual contains a det aile d de scription of the authentication application on the a710x family product. it ou tlines the interface description including the apdu description and a description how to use the applet. 3. these documents are available under nda 4. where xx refers to the last version; e.g. 10 refers to version 1.0
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 6 of 20 nxp semiconductors a710x family secure authentication microcontroller 1.10 trust provisioning service the a710x family is delivered with pre-program med, die-specific keys and certificates which are being generated and programmed in a certified (common criteria) secure nxp semiconductors internal environment with mast er keys securely stored in hsms (hardware secure modules). additional authentication software for the host (host-mcu or remote server) can also be incl uded as part of the solution. nxp semiconductors offers a pre-personaliz ation s service where customer specific initialization data can be preprogrammed. this data can be die individual card manager keys, symmetric des-or aes keys, random data , x509 certificates, rsa signing keys or any other constant data like application code. 1.11 a710x family naming conventions the following table explains the naming conventions of the commercial product name of the a710x family products. every a710x family product gets assigned such a commercial name, which includes also customer and application-specific data. the a710x family commercial names have the following format. a710xagpp(p)/mvsrrff the ?a710? is a constant, all other letters a r e variables, which are explained in the following table 1 . table 1. a710x commercial name format variable meaning values description x ic hardware specification code 1 standard operational ambient temperature: ? 25 ?c to +90 ?c ? i 2 c and spi interface supported 2 standard operational ambient temperature: ? 40 ?c to +90 ?c ? i 2 c and spi interface supported 3 standard operational ambient temperature: ? 25 ?c to +90 ?c. ? i 2 c and uart interface supported a embedded operating system code a jcop v2.4.2 r0.95 c jcop v2.4.2 r1 z custom rom coded product g embedded application fi rmw are (applet) code g generic, no application layer firmware (i.e. jcop apple ts) pre-installed c customized, customer applet pre-installed in rom or eeprom a application firmware implementing generic x50 9 based client authentication pp(p) package type code see ta b l e 3 m manufacturing site code t v silicon version code 0
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 7 of 20 nxp semiconductors a710x family secure authentication microcontroller 1.12 security features the a710x family security concept is combining a comprehensive portfolio of nxp semiconductors security measures which is pr otecting the chip against all types of attacks. all in all there are more than 100 security features in an nxp semiconductors security chip to protect against attacks from outside. nxp semiconductors apply their extensive knowledge of chip security to ha rden the chip against any kinds of attacks. the counter measures against reverse engine ering att a cks i.e. the dedicated security cpu designed in asynchronous handshaking circuit technology, the very dense sub-micron 5-metal-layer 0.14 ? m technology, the nxp glue logic and active shielding technology are prov iding highest level of attack resilie nce which is unique in the market. secure fetch technology will significantly enhance the chip hardw are security for a cert ain class of light and laser attacks to t he chip hardware. more specifically, secure fetch offers increased protection against attacks with higher spatial resolution and against both those with shorter and with longer light pulses; both with single and with multiple pulses. it protects both the device memory and code fetching operations from rom, ram and eeprom, greatly increasing the probability that fault injection atta cks are detected. this unique security technology offers increased protection against future attack scenarios with light and laser sources, fac ilitating the developmen t of highly secure software applications for customers. the a710x family security concept includes de dicated hw measures to protect against any kind of leakage attacks. the triple-des coprocessor provides a high level of leak-resistance to 1st order dpa, thus equally well resilient against all kinds of leakage attacks. the a710x family incorporates inherent and os controlled security features: ? secure fetch technology, protecting code fetches from rom, ram and eeprom ? dedicated security cpu designed in asynchronous handshaking circuit technology ? high dense sub-micron 5-metal-layer 0.14 ? m cmos technology, ? nxp glue logic ? active shielding ? enhanced security sensors ? l ow and high temperature sensor (for a7101 and a7103 only) ? l ow and high supply voltage sensor ? single fault injection (sfi ) attack detection ? l ight sensors (incl. integrated memory light sensor functionality) s silicon version subcode b rr rom code id ff fabkey id table 1. a710x commercial name format variable meaning values description
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 8 of 20 nxp semiconductors a710x family secure authentication microcontroller 1.13 security licensing nxp semiconductors has obtained a patent license for spa and dpa countermeasures from cryptography research incorporated (cri). this license covers both hardware and software countermeasures. it is important to customers that countermeasures within the operation system are covered under this license agreement with cri. further details can be obtained on request.
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 9 of 20 nxp semiconductors a710x family secure authentication microcontroller 2. features and benefits 2.1 standard family features ? high reliable eeprom for both data st orage and program execution: 20 kb ? dat a retention time: 25 years minimum ? end urance: 500,000 cycles minimum ? ded icated secure_mx51 mcu (memory extended/enhanced 80c51) ? pub lic key cryptography (pkc) coproc essor supporting rsa, elgamal, dss, diffie-hellman, guillou-quisquater , fiat-shamir and elliptic curves ? rsa sup p ort for the key lengths up to 4096-bit ? elliptic c u rve over gf(p) cryptograph y with key lengths up to 544-bit ? sing le des (56-bit) and triple des with 2 or 3 keys (112-bit- or 168-bit), encryption a nd decryption in ecb, cbc and cbc-mac mode ? high-speed aes coprocesso r (128-bit p arallel pr ocessing aes engine) ? l ow-power true-random number generator (trng) in hardware, ais-31 compliant ? sha1, sha-224 and sha-256 ? on-ch ip key generation ? crc calculations ? l ow-power design using nxp semiconductors? handshaking technology ? w ake-up from sleep mode by any i 2 c communication request ? 40 ? a typical sleep mode current with i 2 c pads operated in tristate mode, don?t obstructing the bus lines ? 10 ? a maximal deep sleep mode current with i 2 c pads operated in tristate mode, don?t obstructing the bus lines ? inter nally generated cpu clock (typical 31 mhz) ? 1. 62 v to 3.6 v operating voltage range ? br oad spectrum of delivery types ? wa fers ? wl-cs p package ? smd p ackages 2.2 product-specific features ? a7101 ? ? 25 ? c to +90 ? c operational ambient temperature ? 4 00 kbit/s i 2 c fast-mode interface (master and slave) ? 2 mbit four wire spi interface (slave) ? a7102 ? ? 40 ? c to +9 0 ? c operational ambient temperature ? 4 00 kbit/s i 2 c fast-mode interface (master and slave) ? 2 mbit four wire spi interface (slave) ? a7103 ? ? 25 ? c to +9 0 ? c operational ambient temperature ? 1 11 kbit/s one-wire interface according to ref. 16 ? 4 00 kbit/s i 2 c fast-mode interface (master and slave)
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 10 of 20 nxp semiconductors a710x family secure authentication microcontroller 3. applications the a710x family is a complete embedded security platform for mobile phones, portable devices, computing and consum er electronic devices, and embedded systems where a strong security infrastructure is required. th e a710x family provides an outstanding level of security, while overcoming the challeng es of performance, power consumption and solution footprint. its flexible architecture of fers brand owners and device manufacturers a robust solution that can be tailored to meet today?s demanding embedded security requirements. the a710x family can be used in various host platforms and host operating systems to secure a broad range of applications. the a710x family is offered as a turnkey soluti on th at provides customers easy integration of authentication solutions into their end pr oducts. minimal impact on the performance of end-products is achieved through high-speed, low power consumption ics that feature the industry standard i 2 c, spi and uart interfaces. the flexibility of the a710x family solution allow s for fast a nd convenient customization of specific solutions or implementations. 3.1 application areas ? embedded security ? cou nterfeit protection of hardware and software ? anti-cloning ? br and integrity of original goods ? profile of service ? conditional acc e ss to soft ware, content and features ? secure access to on line services ? device identit y ? sig ning transactions ? secur e machine to machine (m2m) communication 4. quick reference data table 2. quick reference data symbol parameter conditions min typ max unit v dd supply voltage 1.62 - 3.6 v eeprom t ret retention time t amb = +55 ?c 25 - - years n endu(w) write endurance under all operating conditions 5 ? 10 5 - - cycles
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 11 of 20 nxp semiconductors a710x family secure authentication microcontroller 5. ordering information [1] a = a or c, g = g, c or a, according to the a710x family type classifi cation see section 1.11 ? a710x family naming conventions ? table 3. ordering information type number [1] package name description version a7101agus/... ffc 8 inch wafer (sawn; 250 ? m thickness; on fi lm frame carrier; electronic fail die marking according to secsii format) not applicable a7102agus/... a7103agus/... a7101aguk/... wlcsp12 wafer level chip scale package, 12 bumping, body 2.1 ? ? 2.1 ? ? 0.6 mm; ? 0.5 mm ball pitch not applicable a7102aguk/... a7103aguk/... a7101agt1/... so-8 plastic small outline package, body 4.9 ? ? 3.9 ? ? 1.75 mm; 1.27 mm pin pitch, 8 l eads sot096-1 a7102agt1/... a7103agt1/... a7101agtk2/... hvson-8 plastic thermal enhanced very thin small outline package; no leads; 8 te rmi nals; body 4? ? 4 ? ? 0.85 mm sot909-1 a7102agtk2/... a7103agtk2/... a7101aghn1/... hvqfn32 plastic thermal enhanced very thin quad flat package; no leads, 32 terminals; body 5 ? ? 5 ? ? 0.85 mm sot617-3 a7102aghn1/... a7103aghn1/... a7101aghn2/... hvqfn20 plastic thermal enhanced very thin quad flat package; no leads, 20 terminals; body 4 ? ? 4 ? ? 0.85 mm sot917-1 a7102aghn2/... a7103aghn2/...
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 12 of 20 nxp semiconductors a710x family secure authentication microcontroller 6. block diagram (1) for more details see ref. 5 figure 3.4 page 36 (2) for more details see ref. 6 (3) for more details see ref. 6 (4) for more details see ref. 16 fig 1. a710x family block diagram with jcop os application layer applet n global platform 2.1.1 other services scspi protocol implementation (3) aes coprocessor eeprom rom ram interface secure mx51 cpu memory management unit (mmu) pki coprocessor famexe triple-des coprocessor rst_n vcc vss spi_miso/i 2 c_sda spi_mosi/i 2 c_scl spi_nss/uart spi_clk hardware layer platform a710x sc1w protocol implementation (4) sci 2 c protocol implementation (2) java card virtual machine (jcvm) i/o network communication transaction management applet management system classes installer java card runtime environment 3.0.1 classic (1) card operating system layer jcop v2.4.2 extensions framework classes apis (java card 3.0.1 classic apis) applet 1 applets applet 2 aaa-007651
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 13 of 20 nxp semiconductors a710x family a710x secure authentication microcontroller fig 2. a710x family block diagram famexe enhanced public key coprocessor e.g. rsa, ecc eeprom 20 kb data and program memory protected linear address mapping secure_mx51 cpu rom spi interface block programmable io spi_miso/i 2 c_sda spi_mosi/i 2 c_scl spi_nss spi_clk 196 kb program memory i 2 c interface block universal asynchronous receiver/ transmitter ram 6144 b data memory timers security sensors reset genereation voltage regulator vcc vss crc16 16-bit t0 16-bit t1 fast rng triple-des coprocessor aes coprocessor a710x rst_n aaa-007652
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 14 of 20 nxp semiconductors a710x family secure authentication microcontroller 7. limiting values [1] pads vcc, vss, rst_n, spi_nss/uart_io, spi_miso/i2c_sda, spi_clk, spi_mosi/i2c_scl [2] mil standard 883-d method 3015; human body model; c = 100 pf, r = 1.5 k ? ; t amb = ?25 ? c to +85 ? c. [3] jesd22-c101, jedec standard field induced charge device model test method. [4] depending on appropriate thermal resistance of the package. table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to vss (gro und = 0 v). symbol parameter conditions min max unit v dd supply voltage ? 0.3 +4.6 v v i input voltage any signal pad ? 0.3 +4.6 v i i input current pad spi_nss/uart_io, spi_miso/i2c_sda, sp i_clk, spi_mosi/i2c_scl - 10 ma i o output current pad spi_nss/uart_io, spi_miso/i2c_sda, sp i_clk, spi_mosi/i2c_scl - 10 ma i lu latch-up current v i < 0 v or v i > v dd - 100 ma v esd electrostatic discharge voltage human body model (hbm) [1] [2] ? 2.0 kv charge device model (cdm) [1] [3] ? 500 v p tot total power dissipation [4] - 1 w t stg storage temperature ? 55 +125 ?c
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 15 of 20 nxp semiconductors a710x family secure authentication microcontroller 8. abbreviations table 5. abbreviations acronym description aes advanced encryption standard api application programming interface cbc cipher-block chaining crc cyclic redundancy check des digital encryption standard dpa differential power analysis dss digital signature standard ecb electronic codebook ecc elliptic curve cryptography eeprom electrically erasable programmable read-only memory gf galois function i/o input/output mac message authentication code md5 message-digest algorithm 5 mmu memory management unit os operating system pkc public key cryptography pki public key infrastructure rsa rivest, shamir and adleman sfi single fault injection sha secure hash algorithm smd surface mounted device spa simple power analysis spi serial peripheral interface
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 16 of 20 nxp semiconductors a710x family secure authentication microcontroller 9. references [1] oracle java card 3.0.1 classic http://www.oracle.com/technetwork/ java/javacard/overview/index.html [2] global platform consortium: globalplatfo rm card specification 2.1.1, march 2003 http://www.globalplatform.org/ [3] globalplatform consortium: globalplatform; card specification 2.1.1 amendment a, march 2004 [4] i 2 c-bus specification and user manual, rev. 0.3 ? june-19-2007, nxp semiconductors [5] java card technology for smart cards, zhiqun chen, isbn 0-201-70329-7 [6] sci 2 c protocol specification, rev. 2.0 ? aug-04-2010, nxp semiconductors [7] sc-spi protocol specification, rev. 1.0 ? ma r-01-2011, nxp semiconductors [8] hardware data sheet a710x family, secure authentication microcontroller, doc u ment number docid 2164xx 5 , nxp semiconductors [9] a710x family with jcop 2.4.2 r1, secure authentication microcontroller, document nu mbe r 2366xx 5 , nxp semiconductors [10] user manual jcop 2.4.2 r1 for a7 fa mily , jcop v2.4.2 re vision 1.0 secure embedded mcu operating system, document number 2318xx 5 , nxp semiconductors [11] admin manual jcop 2.4.2 r1 for a7 fa m ily , jcop v2.4.2 revision 1.0 secure embedded mcu operating system, document number 2319xx 5 , nxp semiconductors [12] application note, device authenticatio n apdu s p ec - fs1.1, document number 2185xx 5 , nxp semiconductors [13] application note, device authentication ar ch itecture, application note for feature set fs1.1, document number 2154xx 5 , nxp semiconductors [14] application note, x.509 device cert ificate f o rmat, document number 2119xx 5 , nxp semiconductors [15] application note, device authenticat io n host library api, document number 2196xx 5 , nxp semiconductors [16] sc1w protocol specification, rev. 1.1, nxp semiconductors [17] sot909-1; hvson8; reel pack; ordering code (12nc) ending 118; packing inf o rmation; rev. 2 ? 19 april 2013 5. where xx refers to the last version; e.g. 10 refers to version 1.0
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 17 of 20 nxp semiconductors a710x family secure authentication microcontroller 10. revision history table 6. revision history document id release date data sheet status change notice supersedes a710x_fam_sds v.3.5 20131101 product short data sheet a710x_fam_sds v.3.4 modifications: ? updated storage temperature in table 4 ? limiting values ? on page 14 a710x_fam_sds v.3.4 20130809 product short data sheet a710x_fam_sds v.3.3 modifications: ? inserted a7103 product type supporting uart communication ? reference to hvson8 packing information added ? inserted electrostatic discharge voltage (charge device model) in table 4 ?limiting values? on page 14 a710x_fam_sds v.3.3 20130315 product short data sheet a710x_fam_sds v.3.2 modifications: ? chapter 7 ?pinning information? removed from product short data sheet a710x_fam_sds v.3.2 20130128 product short data sheet a710x_fam_sds v.3.1 modifications: ? so8 pinning figure corrected. see also figure 8 ?pin configuration for so-8 (sot96-1)? on page 16 a710x_fam_sds v.3.1 20121213 product short data sheet a710x_fam_sds v.3.0 modifications: ? hvqfn32 pinning corrected. spi_nss is connected to pin 3 and pin 2 is not connected. see also figure 7 ?pin configuration for hvqfn32 (sot617-3)? on page 15 and table 7 on page 15 ? hvson8 package (sot685-1, 5 mm ? 6 mm) removed from table 3 ?ordering information? on pag e 11 ? footnote about availabilty of hvqfn20 pack age removed. hvqfn20 package is available. ? defined maximum input and output currents in table 4 ?limiting values? on page 14 a710x_fam_sds v.3.0 20121024 product short data sheet a710x_fam_sds v.2.0 modifications: ? product version a710x_fam_sds v.2.0 20111005 preliminary short data sheet - modifications: ? initial version
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 18 of 20 nxp semiconductors a710x family secure authentication microcontroller 11. legal information 11.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of mu ltiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 11.2 definitions draft ? the document is a draft versi on only . the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet wit h the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product dat a sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 11.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be lia ble fo r any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason what soe ver, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes t o information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, aut hori zed or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these prod uct s are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and pr oduct s using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liabil i ty related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in th e absolute maximum ratings system of iec 60134) will cause permanent damag e to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors prod uct s are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agre ement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or co nstr ued as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objec tive specif icati on for product development. preliminary [short] data sheet qualification this document contains data from t he preliminary specification. product [short] data sheet production this document contains the product specification.
a710x_fam_sds all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product short data sheet ? company public rev. 3.5 ? 1 november 2013 195735 19 of 20 nxp semiconductors a710x family secure authentication microcontroller export control ? this document as well as the item(s) described herein may b e subject to export control regu lations. export might require a prior authorization from competent authorities. quick reference data ? the quick reference data is an extract of the pro duct dat a given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly st at es that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he pro duct for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. translations ? a non-english (translated) version of a document is for ref e rence only. the english version shall prevail in case of any discrepancy between the translated and english versions. 11.4 licenses 11.5 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. fabkey ? is a trademark of nxp b.v. i 2 c-bus ? logo is a trademark of nxp b.v. 12. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com ics with dpa countermeasures functionality nxp ics containing functionality impleme nti ng countermeasures to differential power analysis and simple power analysis are produced and sold under applicable license from cryptography research, inc.
nxp semiconductors a710x family secure authentication microcontroller ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com ? for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 1 november 2013 195735 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 13. tables table 1. a710x commercial name format . . . . . . . . . . . . .7 table 2. quick reference data . . . . . . . . . . . . . . . . . . . . 10 table 3. ordering information . . . . . . . . . . . . . . . . . . . . . 11 table 4. limiting values . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6. revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 14. figures fig 1. a710x family block diagram with jcop os. . . . .12 fig 2. a710x family block diagram . . . . . . . . . . . . . . . . 13 15. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 1.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 cryptographic hardware co processors . . . . . . . 3 1.2.1 pki coprocessor . . . . . . . . . . . . . . . . . . . . . . . 3 1.2.2 triple-des coprocessor . . . . . . . . . . . . . . . . . . 3 1.2.3 aes coprocessor . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.5 universal asynchronous receiver/transmitter (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.6 general-purpose io ports. . . . . . . . . . . . . . . . . 4 1.7 optional on-chip cryptographic library . . . . . . . 4 1.8 optional on-chip oper atin g system fi rmware: jcop 2.4.2 (a710xc) . . . . . . . . . . . . . . . . . . . . 4 1.9 optional x509 certif icate-base d client authentication . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.10 trust provisioning service . . . . . . . . . . . . . . . . . 6 1.11 a710x family naming conven tions . . . . . . . . . . 6 1.12 security features. . . . . . . . . . . . . . . . . . . . . . . . 7 1.13 security licensing . . . . . . . . . . . . . . . . . . . . . . . 8 2 features and benefits . . . . . . . . . . . . . . . . . . . . 9 2.1 standard family features . . . . . . . . . . . . . . . . . . 9 2.2 product-specific features . . . . . . . . . . . . . . . . . 9 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 application areas . . . . . . . . . . . . . . . . . . . . . . 10 4 quick reference data . . . . . . . . . . . . . . . . . . . . 10 5 ordering information . . . . . . . . . . . . . . . . . . . . 11 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 8 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 11 legal information. . . . . . . . . . . . . . . . . . . . . . . 18 11.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 11.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11.4 licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.5 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 19 12 contact information . . . . . . . . . . . . . . . . . . . . 19 13 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 14 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 15 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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